The invention relates to memory devices and more particularly to phase change memory (PCM) devices and methods for manufacturing the same.
Phase change memory devices are non-volatile, highly readable, highly programmable, and require a lower driving voltage/current. Current trends in phase change memory development are to increase cell density and reduce current density thereof.
Phase change material in a phase change memory device has at least two solid phases, a crystalline state and an amorphous state. Transformation between these two phases can be achieved by changing the temperature of the phase change material. The phase change material exhibits different electrical characteristics depending on its state. For example, in the amorphous state the material exhibits a higher resistivity than in the crystalline state. Such phase change material may switch between numerous electrically detectable conditions of varying resistivity on a nanosecond time scale with the input of pico joules of energy. Chalcogenide material is a popular and widely used phase change material in modern phase change memory technology. Since phase change material allows a reversible phase transformation, memory bit status can be distinguished by determining the phase of the phase change material in the memory bit.
FIG. 1 partially shows a cross sectional view of a conventional phase change memory (PCM) cell. As shown in FIG. 1, an isolation structure 12 is located at a predetermined region of a semiconductor substrate 10 to thereby define an active region. A source region 16a and a drain region 16b are disposed in and separated by a distance in the active region. A gate 14, functioning as a word line, is disposed across the active region between the source region 16a and the drain region 16b. The gate 14, the source region 16a and the drain region 16b form a transistor. The semiconductor substrate 10 having the transistor thereon is covered with an insulating layer 20. An interconnect line 24 is disposed over the insulating layer 20. The interconnect line 24 is electrically connected to the drain region 16b through a contact hole penetrating the insulating layer 20. Another insulating layer 22 covers the interconnect line 24. A heating plug 18 is disposed in the insulating layers 22 and 20, electrically contacting the drain region 16b. A patterned phase change material layer 28 and a top electrode 34 are sequentially stacked over the insulating layer 22, wherein a bottom surface of the phase change material layer pattern 28 is in contact with the heating plug 18. Another insulating layer 26 is disposed on the insulating layer 22. A bit line 36 is located on the insulating layer 26 and is in contact with the top electrode 34.
In a write mode, the transistor is turned on and a large current flows through the heating plug 18, thus heating an interface between the phase change material layer 28 and the heating plug 18, thereby transforming an active portion 30 of the phase change material layer 28 into either the amorphous state or the crystalline state depending on the length of time and amount of current flowing through the heating plug 18.
FIG. 2 partially shows a cross sectional view of a conventional phase change memory cell as illustrated in U.S. Pat. No. 5,789,758 issued to Reinberg. As shown in FIG. 2, a phase change memory cell 90 includes a plurality of sequentially stacked bottom electrode contact layers 55, 60 and 65 embedded in an oxide layer 35. The bottom electrode contact layer 65 comprises a phase change material. An opening 70 is formed in the oxide layer 35 and the opening 70 exposes a part of the bottom electrode contacting layer 65. A phase change material layer 75, a upper contact electrode layer of carbon 80 and a upper contact electrode of molybdenum 85 are sequentially formed over the oxide layer 35, wherein the phase change material layer 75 fills the opening 70 and physically contacts the phase change material in the underlying bottom electrode contact layer 65. The phase change material layers, upper contact electrode of carbon 80 and the upper contact electrode of molybdenum 80 are partially covered by an oxide layer 95. An aluminum conductor 100 is formed over the oxide layer 95. The aluminum conductor 100 is partially disposed in the oxide layer 95 and electrically contacts the upper contact electrode of molybdenum 85. A top encapsulating layer 105 is formed over the aluminum conductor 100. In a write mode, the portion of the phase change material layer 75 in an active region A in the opening 70 of the phase change memory cell illustrated in FIG. 2 is heated, thereby transforming the portion of the phase change material layer 27 therein into either the amorphous state or the crystalline state depending on the length of time and amount of current flowing through the phase change material layer 27.